Keynote Talk

The Argo Network on Chip – Microarchitecture, Key Features and Lessons Learned

Jens Sparsø

Technical University of Denmark


Today, most digital chips are multi-core designs that use some form of packet switched network-on-chip (NoC) to provide the necessary communication among processor cores, memories, IO-devices etc. In the domain of general-purpose computing, the key focus is on optimizing for bandwidth and latency in the typical case. In the embedded systems domain requirements are typically more diverse and if real time applications are to be supported, the ability to give guarantees on throughput and latency in the worst-case becomes a primary concern.

This talk will present the Argo NoC that is designed to support message-passing in a multicore platform intended for hard real-time systems [1]. Aiming for a small hardware cost we decided for a design based on time-division-multiplexing of resources, static scheduling of traffic and source routing of packets. Argo avoids all forms of run-time arbitration, flow control and buffering – features that account for most of the hardware cost of a typical NoC. In Argo, data is transferred directly from the private memory of the sending processor core and into the private memory of the receiving processor core, and in this process the network of routers and links merely provides a pipelined path for each traffic flow. The talk will introduce the microarchitecture of Argo, present some key features (scheduling and timing organization) in more depth and finally discuss some lessons learned.

In the field of computer networks, the conventional designer thinking is one of layering, encapsulation and clean interfaces. One of the lessons from our work is that, this thinking can actually be what causes the need for buffering and flow control. Other observations, perhaps more subjective, are that NoC- research tend to focus more on functionality than on the hardware cost of implementing it, and that results on hardware cost are often difficult to compare.

This relate to the following point that is best made using an analogy: During the 1980’s computer architectures changed from CISC to RISC. Exploiting the emerging VLSI technology of that time, RISC processors could be made smaller and faster. The principle “provide primitives not solutions” captured some essence of this change. Are we designing NoCs that provide solutions or NOCs that provide primitives?


Biography: Jens Sparsø (Member IEEE) is full professor at the Technical University of Denmark (DTU). His research interests include: design of digital circuits and systems, design of asynchronous circuits, low-power design techniques, application-specific computing structures, computer organization, multi-core processors, and networks-on-chips -- in short hardware platforms for embedded and cyber-physical systems.

He has published more than 90 refereed conference and journal papers and is coauthor of the book “Principles of Asynchronous Circuit Design – A Systems Perspective” (Kluwer, 2001), which has become the standard textbook on the topic.  He received the Radio-Parts Award and the Reinholdt W. Jorck Award in 1992 and 2003, in recognition of his research on integrated circuits and systems. He received the best paper award at ASYNC 2005, and one of his papers was selected as one of the 30 most influential papers of 10 years of the DATE conference.

[1]The Argo NoC is used in the T-CREST multicore platform. The entire design and tools to support it (compiler, scheduler and worst-case execution time analyzer) are available in open source hosted at GitHub: