Keynote Talk

Architecting Chiplet-based Systems

Natalie Enright Jerger

University of Toronto - Department of Electrical and Computer Engineering


Moore's law has conventionally enabled increasing integration; however, fundamental physical limitations have slowed the rate of transition from one technology node to the next, and the costs of new fabrication facilities are skyrocketing. Despite this, emerging applications such as machine learning have a seemingly insatiable appetite for more compute and memory bandwidth. The maturation of die stacking enables the continued integration of system components in traditionally incompatible processes. A key application of die-stacking is silicon interposer-based integration of multiple 3D stacks of DRAM, potentially providing several gigabytes of in-package memory. The use of an interposer presents new opportunities; in particular, if one has already paid for the interposer for the purposes of memory integration, any additional benefits from exploiting the interposer could come at a relatively small incremental cost. In this talk, I will describe the exciting opportunities enabled though interposer-based integration including our recent work on reduced manufacturing costs. I will also explore some of the key challenges associated with communicating data across chiplet boundaries through the interposer.

Biography: Natalie Enright Jerger is a Professor of Electrical and Computer Engineering at the University of Toronto. Prior to joining the University of Toronto, she received her PhD from the University of Wisconsin-Madison in 2008. She received her Bachelor's degree from Purdue University in 2002. She currently holds the Canada Research Chair in Computer Architecture. She is a recipient of the Ontario Ministry of Research and Innovation Early Researcher Award in 2012, the 2014 Ontario Professional Engineers Young Engineer Medal, the 2015 Borg Early Career Award and a 2015 Alfred P. Sloan Fellowship. She served as the program co-chair of the 7th Network-on-Chip Symposium and as the program chair of the 20th International Symposium on High Performance Computer Architecture. She is currently serving as the Vice Chair for ACM SIGARCH. Her current research explores on-chip networks, approximate computing, IoT architectures and machine learning acceleration. In 2017, she co-authored the second edition of the Computer Architecture Synthesis Lecture on On-Chip Networks with Li-Shiuan Peh and Tushar Krishna. She is passionate about increasing the representation of women in computing, particular in computer architecture. She currently chairs the organizing committee for the Women in Computer Architecture group (WICARCH) and is co-chair of ACM’s new Council on Diversity and Inclusion.