Unconventional computing and what it means for the future of interconnects


Panel Moderators and Co-Chairs: 
Ishan Thakkar, University of Kentucky
Amlan Ganguly, Rochester Institute of Technology

The growing performance needs of modern data-driven applications related to the Internet-of-Things (IoT), Big Data, and Artificial Intelligence (AI) result in demand for increasingly higher levels of computational complexity, storage capacity, and communication performance in computing devices. Fast and efficient interconnects among processor cores and/or memory subsystems in high-end processing platforms have proven to be an expensive and elusive objective over more than a decade. Moreover, due to the rapidly growing deployment of computing devices across the globe, the total annual energy consumption for computing is projected to account for up to 20-25% of the annual primary energy consumption globally, by early in the next decade. Therefore, to meet the proliferating demands for computing without overshooting the global energy budget, scaling up the performance of the future computing systems with significant improvement in their energy-efficiency is of paramount importance. However, the computing industry will no longer be able to scale up computing capability and energy-efficiency using the basic approach of scaling down the transistor feature sizes or improving the bandwidth of conventional interconnection systems. To address this issue, significant research efforts have focused on design of novel and non-traditional interconnects. Recently, that effort is augmented and rivaled by the research on non-conventional or non-von Neumann architectures for computing. 

To unfold various aspects of the cutting-edge research in these unconventional paradigms of computing, especially to unpack what the impacts of these new paradigms of computing would be on the interconnection subsystems of future computing systems, we organized a panel entitled “Unconventional Computing and What It Means for the Future of Interconnects” as part of the IEEE/ACM International Workshop on Network-on-Chip Architectures (NoCArc) 2020. The following panelists participated in the panel, and they shed light on the topics of their respective expertise as listed below.

Marc Riedel, University of Minnesota — [DNA Computing]

Sudeep Pasricha, Colorado State University — [Photonic Computing and Interconnects]

Abu Sebastian, IBM Zurich — [Processing in Memory]

Rajeev Balasubramonian, University of Utah — [Accelerators]

Masoud Babaie, TU Delft — [Quantum Computing]

Baris Taskin, Drexel University — [Wireless Interconnects]