AREAS OF INTEREST

The workshop will focus on issues related to the design, analysis, and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to:

NoC Architecture and Implementation

• Topologies, routing, and flow control

• Managing QoS

• Reliability issues

• Security issues

• Design methodologies and tools

NoC Analysis, Optimization, and Verification

• Power, energy, and thermal issues

• Benchmarking and experience with NoC-based systems

• Modeling, simulation, and synthesis

• Verification, debug, and test of NoCs and NoC-based systems

• Metrics and benchmarks

NoC Applications

• • Mapping of applications onto NoCs

  • Real and industrial NoC case studies

  • NoCs for FPGAs, structured ASICs, CMPs, and MPSoCs

  • NoC designs for heterogeneous systems

NoC at System-level

• Design of memory subsystem

• NoC support for memory and cache access

• OS support for NoCs

• Programming models including shared memory, message passing, and novel programming models

• Large-scale systems (datacenters and supercomputers) with NoC-based systems as building blocks

Emerging NoC Technologies

• Wireless, Optical, and RF

• NoCs for 3D and 2.5D packages

• Approximate computing for NoCs and NoC-based systems

• Chip-to-Chip Interconnects

Machine learning (ML) and NoC-based systems

• Novel Interconnects for ML systems/accelerators

• Memory access for NoC-based ML systems

• NoC-based ML algorithm design

Besides regular papers, papers describing work in progress or incomplete but sound new innovative ideas related to the workshop theme are also encouraged.